[HVM] Fix an error when read from APIC registers like IRR, ISR and TMR.

[HVM] Fix an error when read from APIC registers like IRR, ISR and TMR.
From SDM3 spec, for APIC registers, all 32-bit registers should
be accessed using 128-bit aligned 32bit loads or stores.
And wider registers (64-bit or 256-bit) must be accessed using
multiple 32-bit loads or stores.

In old APIC virtualization code, we use IRR, ISR and TMR which are
256-bit registers as contiguous bit maps other than multiple 32-bit.

So guest always fetch error values.

Original patch was:
 * Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>
 * Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
 * Signed-off-by: Eddie Dong <eddie.dong@intel.com>

Signed-off-by: Keir Fraser <keir@xensource.com>